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CXB1549Q
Laser Diode Driver
Description The CXB1549Q is a high-speed monolithic Laser Diode Driver/Current Switch with ECL/PECL input level. Open collector outputs are provided at the output pins (Q, QBX) and have the capacity of driving modulation current of 50mAp-p at a max. data rate of 1.25Gbps (Min.). Along with the modulation current generator there is the laser diode bias generator which has capacity of sourcing up to 60mA (Bias). The laser diode current can be controlled by either a voltage or current into the bias adjust pin (BiasAdj) and the bias set pin (SBias), depending on how these pins are configured. Control of the diode bias current is achieved through the APC (Automatic Power Control) circuitry. In order to avoid having a large current go through the laser diode, this IC also provides an Activity detector and Power on Reset functions for Laser Safety. The Activity detector circuit detects data edge transitions and if no data transition occur after a certain time period, then both the modulation and bias current are shutdown. The Power on Reset circuit holds the modulation and bias current off for a set period of time while the system power is applied. Additionally, this IC has an internal Duty Cycle correction circuit that can control the falling edge of the input pulse up to a maximum of 0.2ns (Min.). Features * Maximum data rate (NRZ): 1.25Gbps * Power on Reset function * Alarm and Shutdown function * Signal Duty cycle correction * Automatic Power Control (APC) for bias current * Activity detector function for laser safety * Power indicate function * Differential PECL inputs or AC coupled inputs 40 pin QFP (Plastic)
Application * Gbit-ethernet: 1.25Gb/s * SONET/SDH: 622Mb/s * Fibre channel: 532Mb/s,1.062Gb/s Absolute Maximum Ratings * Supply voltage Vcc - VEE
* Input voltage VIN * Differential input voltage | VD - VDB | 0 to 2.5 * Bias output current 0 to 80 * Modulation output current 0 to 70 * SBias input/output current 0 to 5 * Input bias control current Iset (Ibiasadj) 0 to 5 * Input bias control voltage Vset (Vbiasadj) 0 to 3 * Storage temperature Tstg -65 to +150 Recommended Operating Conditions * DC power supply voltage 3.14 to 3.46 Vcc - VEE * Operating ambient temperature Ta -40 to +85 Structure Bipolar silicon monolithic IC
-0.3 to +6.0 VEE to Vcc
V V V mA mA mA mA V C
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98313A8X-PS
CXB1549Q
Block Diagram and Pin Assignment
LDAlmB
Indicate
VCC2
RSB
Tset
VBB
RS
30
29
28
27
26
25
24
23
22
21
LDAlm 31
Reference Generator
VBB Generator 20 ADCDis 19 TM 18 NC Duty Cycle Cont In_ALM 17 Timer
SDN 32 SDNB 33 VREF 34 TEST_PIN 35 VCC3 36 CapZ 37 VEE3 38 APCOut 39 RsetPD 40 Bias Circuit Power on Reset VREF
VEE2 16 CompB 15 CompA DRV Cont 14 DrvAdj 13 DrvMon 12 VEE1 11 VCC1 9 VEE1 10 VEE1
1 VCC4
2 VEE4
3 BiasAdj
4 SBias
5 Bias
6 VEE5
7 Q
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QBX
DB 8
D
CXB1549Q
Pin Description Pad No. 1 2 Symbol VCC4 VEE4 Typical voltage [V] DC 3.3 0 AC Equivalent circuit Description Positive power supply pin for APC circuit. Negative power supply pin for APC circuit.
VCC
3
BiasAdj
1.5 to 0 0mA to 2.5mA 0mA to 60mA 0 6mA to 30mA1 6mA to 50mA2 6mA to 30mA1 6mA to 50mA2
4
5
Sets Laser bias current pin. Sets Laser bias current or monitor pin. Laser bias current output. Open collector output. Negative power supply pin for Bias circuit. Laser modulation current output. Open collector output. Complementary current output. Q and QBX are not symmetrical output. Please uses Q output for Laser modulation. Negative power supply pin for Driver circuit. Positive power supply pin for Driver circuit. Negative power supply pin for Driver circuit.
4
SBias
3 10pF 240 VEE
30 8
5
Bias
6
VEE5
7
Q
1.3 to 3.3
7
8
8
QBX
1.3 to 3.3
Current Source VEE
9, 10 11 12
VEE1 VCC1 VEE1
0 3.3 0
13
DrvMon
0A to 600A
VCC
Rdrv Rmon 14 13
Sets Laser modulation current (IQ) monitor. IQ is monitored by connecting a resistor (Rmon) to this pin. Sets Laser modulation current (IQ). IQ is controlled by connecting a resistor (Rdrv) to this pin. Please refer to Fig.2.
14
DrvAdj
0A to 600A
150 150 1.3k VEE
1 Ta = -40 to 0C 2 Ta = 0 to +85C
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CXB1549Q
Pad No.
Symbol
Typical voltage [V] DC AC
Equivalent circuit
Description
15
CompA
180pF
VCC 15 16 30pF
16
CompB
VEE
10k
Modulation current driver compensation. Normally, connects 180pF Capacitor across CompA and CompB pins.
VCC Ctimer 17 2.4k 2.1k 2.4k
17
Timer
25A
10pF 200A
VEE
Capacitor port for activity detector (IN_ALM) operation. This pin set the period of inactive time for activity detector. Inactive time is controlled by connecting a capacitor to this pin. Please refer to Fig.6.
18 19
NC TM 1.5
19 GND 21
No Connect pin. Chip temperature monitor pin.
VCC 3.8k 3.8k
20
ADCDis
VEE to VCC (open)
20 VEE
35k 35k 35k 35k 15A
This pad control the activity detector Circuit. High (connected to Vcc or open): an activity detector is disable. Low (connected to GND): an activity detector is enable.
21
VEE2
0
Negative power supply pin for Data input circuit.
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CXB1549Q
Pad No.
Symbol
Typical voltage [V] DC AC 1.6 to 2.4
Equivalent circuit
Description
22
DB
24 300 22 400 300 25 200 10k 10k 21
23
D
1.6 to 2.4
23
200
Differential PECL data inputs pins. These two inputs are internally biased by 10k to VBB.
24 25
VCC2 VBB
3.3 2
600A 600A
Positive power supply pin for Data input circuit. Reference bias voltage. (Option) The analog voltage high impedance output which indicate of whether the optical power of Laser diode is operated normal or not. The power output range has following relationship. High Light Indication; Vo 1.7V Nominal Operation; Vo = 1.2V Low Light Indication; Vo 0.7V Selector for duty cycle control. This pin controls the trailing edge of the input high pulse. Variable delay limit of that is from 0 to 0.2ns. Duty cycle is controlled by connected a resistor value between Vcc and this pin. Please refer to Fig.1.
VCC 50A 100k 26 35A 35A
26
Indicate
0.7 to 1.7
14k VEE
VCC 2.4k 2.4k Rset 27
20pF
27
Tset
70A VEE 220 140
VCC
28
RSB
0.5
29
100A 2.5k 20k 28
29
RS
2.5
VEE
5k
Sets alarm (fail) threshold assert voltage by external resistors for LD_ALARM. Default voltages are RS equal to 2.5V and RSB equal to 0.5V. (Option)
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CXB1549Q
Pad No.
Symbol
Typical voltage [V] DC AC
Equivalent circuit
Description
VCC
30
LDAlmB
0.2 to 3
4.7k 4.7k 30 31
Complementary open collector TTL outputs. Asserted when the fault is detected in the Laser monitor diode circuit.
31
LDAlm
0.2 to 3
VEE
VCC
32
SDN
0 to 3.3
300 32
5k
5k
5k
5k
300 33
Complementary TTL inputs to disable output current. When left open = "High"
60A
33
SDNB
0 to 3.3
VEE
60A
VCC 300 200 34 300
34
VREF
1.7
2.4k
Temperature compensated reference voltage for APC. 1.7V (Constant.)
1.9mA
9.1k VEE
35 36
TEST_ PIN VCC3
OPEN 3.3
Do not connect. Positive power supply IC for Signal Detect circuit.
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CXB1549Q
Pad No.
Symbol
Typical voltage [V] DC AC
Equivalent circuit
Description
VCC Rseries 200 37 3k
37
CapZ
Cap_Z 145A 145A VEE
Capacitor and resistor port for slow start up. This pin controls the initial turn-on time of this chip. (bias and modulation current) The time for this function is set by an external RC network. Please refer to Fig.7. Negative power supply pin for Signal Detect circuit.
38
VEE3
0
VCC
39
APCOut
39
Output pad of APC OPAmp. This signal control to bias adjust pins. (BiasAdj and SBias)
500 VEE
VCC 300 200 40 300
40
RsetPD
1.8mA VEE
Monitor PD connect pad.
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CXB1549Q
Electrical Characteristics DC Electrical Characteristics Item DC Power supply voltage Power supply current Modulation output current range Modulation output voltage range Bias output current range Bias output voltage range Ratio of IB vs. Iset ECL input High voltage ECL input Low voltage Symbol Vdc IEE IQ1 IQ2 VQ IB VB IBvslset VEIH VEIL (VCC = 3.14 to 3.46V, VEE = 0V, Ta = -40 to +85C) Condition VCC - VEE IQ = 0mA, IBIAS = 0mA Ta = -40 to 0C Ta = 0 to +85C Min. 3.14 -76 6 6 VCC - 2 0 VCC - 2 14 VCC - 1.17 VCC - 1.84 2 0 IOH = -10A, RL = 4.7k VCC - 0.1 IOL = 1mA, RL = 4.7k 0 1.5 -500 Typ. 3.3 -59 -- -- -- -- -- 22 -- -- -- -- -- -- 1.7 -- Max. 3.46 -- 30 50 VCC 60 VCC 27 VCC - 0.81 VCC - 1.48 VCC 0.8 VCC + 0.2 0.4 1.9 +500 A V V mA V -- mA Unit V
SDN, SDNB, Reset input High voltage VTIH SDN,SDNB, Reset input Low voltage LDA, LDAB output High voltage LDA, LDAB output Low voltage Reference bias voltage for OP Amp Operating current range of VREF VTIL VTOH VTOL VREF VREFdrv
AC Electrical Characteristics Item Maximum Data Rate Rise time (20 to 80%) Fall time (20 to 80%) Max. variable High pulse width by duty cycle control Symbol fdmax tr tf tdelay
(VCC = 3.14 to 3.46V, VEE = 0V, Ta = -40 to +85C) Condition Min. 1.25 IQ = 20mA, RL = 25 IQ = 20mA, RL = 25 Data rate = 1.25Gbps -- -- 0.2 20 150 -- -- Typ. -- 100 200 -- -- -- -- -- Max. -- -- -- -- -- -- 10 100 s ns Unit Gbps ps
Max. setting time range of IN_Alarm ts_alm Max. setting time range of POR Shut down time Shut down recovery time ts_por tsut_off tsut_on
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CXB1549Q
DC and AC Electrical Characteristics for OpAmp of APC Circuitry Item Input voltage range Output voltage range Input bias current Input offset voltage Input offset Input current Input impedance Output drive current Through rate Open loop gain Unity gain band-width Symbol VIN VO IB VOFF IOFF ZIN IO SR Av funit Condition Min. 1.2 0.6 -- -- -- -- -5.0 -- -- -- Typ. -- -- 7 2.5 0.7 12 -- 1.9 55 20 Max. 2.8 2 -- -- -- -- 1.0 -- -- -- Unit V V A mV A k mA V/s dB MHz
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CXB1549Q
Description of each function block 1. Data Buffer Data Buffer is comprised of the data buffer and delay generator. ECL/PECL data is input to the data buffer at a maximum data rate of 1.25Gbps. This data is buffered and input to the delay circuitry. The delay circuitry adds a delay to the falling edge of the pulse up to a maximum of 0.2ns (Min.). The delay is set by a single external resistor between the delay set pin (Tset-Pin 27) and Vcc. A plot of the high pulse width vs. set resistance (Rset) is shown in Fig. 1. 2. VBB Generator This circuit provides a reference bias voltage to the data buffer for AC coupling inputs. 3. Modulation Current Generator This circuit can sink up to 50mA of current to modulate the laser diode. The modulation current is set by an external resistor to Vcc at modulation current set pin (DrvAdj-Pin 14). There is also a modulation current monitor pin (DrvMon-Pin 13) that allows the IC user to monitor the modulation current. By putting an external fixed resistor between Vcc and DrvMon pin, you can monitor the modulation current by measuring the voltage of DrvMon pin. A plot of the modulation current vs. setting resistance (Rdrv) is shown in Fig. 2. 4. Laser Diode Bias Current Generator This circuit is a very large current source capable of sourcing up to 60mA of current to bias the laser diode on. The circuit is a 22 to 1 current mirror that can be controlled externally two ways. The first of these is to tie the BiasAdj (Pin 3) and SBias (Pin 4) terminals together and inject a current into the two terminals. The Bias (Pin 5) terminal is connected to the laser diode. Laser diode bias current vs. control current (Iset) characteristics is shown in Fig. 3. The second method of controlling the laser diode current is to ties the SBias (Pin 4) terminal to Vcc and tune the BiasAdj (Pin 3) terminal with a voltage source. Varying the voltage at the BiasAdj terminal will vary the current through the laser diode. Laser diode bias current vs. control voltage characteristics is shown in Fig. 4. 5. APC (Automatic Power Control) Circuitry The APC Circuitry is comprised of the window comparator, APC OpAmp, laser diode alarm circuit and the diode power indicator. The APC OpAmp is normally configured as an inverting integrator. The inverting input is connected to the photo diode that monitors the light intensity from the laser diode. The photo diode converts the received light from the laser diode to a current. The output of the OpAmp then drives the laser diode current bias adjust pin, and the laser diode bias set pin is held at Vcc. With the OpAmp configured as an inverting integrator, the OpAmp can tune the diode current inversely to the current in the photo diode. That is to say that if a low current is detected by the photo diode the integrator output goes up causing more bias current to go through the diode. If the photo diode current is high, then the output of the OpAmp will go low causing less bias current to flow through the laser diode. The output of the APC OpAmp drives a window comparator. The function of the window comparator is to detect when the output of the APC OpAmp goes above or below a preset reference voltage for each comparator (RS, RSB). When this happens the comparators outputs cause the laser diode alarm circuit (LDAlm) to go high alerting the system that the laser diode current is either to high or to low. The window comparator also drives the laser diode power indicator circuit (Indicate). This circuit is comprised of two switches and one fixed current sources. When the APC OpAmp output is such that the laser diode bias current is at its nominal set point, the output of the power indicator is at 1.2Vdc. If the APC OpAmp output goes low, the output of the power indicator increases to 1.7Vdc, indicating a high laser diode power condition. If the output of the APC OpAmp goes high, the output of the power indicator drops to 0.7Vdc. Also connected to the output of the window comparator is laser alarm circuitry. This circuit alerts the user of the device when the laser diode power level has risen either twice the normal set power or half the normal set power. A high voltage at the laser diode alarm output indicates an alarm event. The laser diode alarm output is disabled whenever a shutdown event is encountered. - 10 -
CXB1549Q
6. Shutdown and Input Alarm Circuitry This portion of the circuit disables both the modulation current driver and the laser diode bias generator under various conditions. The function block diagram for all of the shutdown mechanisms for the circuit is shown in Fig. 5. Shown below is the signal priority primarily for the reset function. 1) Power on Reset 2) Shutdown, Input Alarm The Shutdown circuit has complementary TTL input to disable output current. Shown below is the desired truth table for the shutdown function. SDN Low Low High High SDNB Low High Low High output current Off On Off Off
The Activity detector (In_ALM) circuit is designed to detect an input pulse transition. If there is no input pulse transition over a period time determined by the user, then the output of the circuit will go high causing the modulation current and laser bias current to be shutdown. Inactive time is set by external capacitor value between Timer pin (Pin 17) and VCC. Inactive time vs. Ctimer is shown in Fig.6. The Power on reset circuit is an inverting comparator that has an external RC network with CapZ pin (Pin 37) that is connected between Vcc and VEE. At power up, the RC begins to charge up towards the reference voltage of the comparator. Since this is an inverting comparator the output will stay high until the capacitor charges above the reference. As long as the comparator output is high, the laser diode is disabled. As soon as the capacitor charges up beyond the reference, the output of the circuit goes low and the laser diode is enabled and ready for normal operation. A plot of the power on reset time vs. capacitance for a 10k resistor (Rseries) is shown in Fig. 7.
SDN SDNB
Shutdown Switch To Modulation and Bias Current shutdown circuits
D DB
In_ALM
Timer ADCDis Power on Reset (CapZ) Power on Reset
Fig.5. Shutdown and In_ALM Functional Block Diagram 7. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. The Tset terminal (27pin) has to be connected through a resistor to Vcc. Do not leave this pin open or connect to Vcc directly. - 11 -
CXB1549Q
DC Electrical Characteristics Measurement Circuit
4.7k
V V
-10 or 1mA 30 4.7k 31 29 28 27
V
2k V
V
26
25
24
23
22
21
V
Reference Generator
VBB Generator 20 19
V
V
32 33 18 Duty Cycle Cont In_ALM 17 0.1F 34 -500 to 35 500A 36 10k 1000pF 38 13 37 Power on Reset DRV Cont 14 VREF 16 180pF 15
V
V
A
V
1k
39 40 12 Bias Circuit 11
1k
1
2
3
4
5
6
7
8
9
10
A A
0 to 2V
A
25
A
3.14 to 3.46V
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CXB1549Q
AC Electrical Characteristics Measurement Circuit
51 4.7k 0.1F
51
0.1F 22 21
30 4.7k 31
29
28
27
26
25
24
23
Reference Generator
VBB Generator 20 19 18 Duty Cycle Cont In_ALM 17 0.1F
32 33 34 100k 35 36 37 1000pF 38 Spectrum analizer 1F 39 40 1F Bias Circuit Power on Reset VREF
16 180pF 15 DRV Cont 14
10k
13 1k
12 11
1
2
3
4
5
6
7
8
9
10
25 3.14 to 3.46V
Oscilloscope 50 input
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Z0 = 50
CXB1549Q
Application Circuit (at VCC = 3.3V, VEE = 0V)
VCC LDAlm LDAlmB 4.7k VCC 100pF 4.7k 30 29 28 Rset 27 26 25 24 23 22 21 Indicate 0.1F PECL input
31
Reference Generator
VBB Generator 20 19 18 Duty Cycle Cont In_ALM 17 Ctimer
SDN SDNB
32 33 34 VCC 35 10k 36 37 38 39 40 Bias Circuit Power on Reset VREF
180pF 16 100pF 15 DRV Cont 14 510 13 Rdry
CapZ
Rf
Cpd
12 11
1
2
3
4
5
6
7
8
9
10
Rs 15 RI lset 5.1 20
Rpd
100pF
0.1F
3.3V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXB1549Q
Example of Representative Characteristics
0.4 0.3 0.2 0.1 IQ [mA] 0 -0.1 -0.2 -0.3 -0.4 0 1 2 3 4 5 Rset [k] 6 7 8 10 40 60
50
Falling edge delay [ns]
30
20
0
0
2
4 6 Rdrv [k]
8
10
Fig. 1. Delay vs. Rset Characteristic at 1ns input data pulse apply
70 60 50 IBIAS [mA] 40 30 20 10 0 IBIAS [mA] 70 60 50 40 30 20 10 0
Fig. 2. Modulation Current (IQ) vs. Rdrv Characteristics
0
0.5
1
1.5 Iset [mA]
2
2.5
3
0.4
0.6
0.8
1 Vset [V]
1.2
1.4
1.6
Fig. 3. Bias Current (IBIAS) vs. Bias adjust current (Iset) Characteristics
70
Fig. 4. Bias Current (IBIAS) vs. Bias adjust voltage (Vset) Characteristics
2.0
60 Power on time [100s] 1 2 2.5 3 Ctimer [nF] 1.5 Shutdown time [s]
50
40
1.0
30
0.5
20
10
0.5
1.5
3.5
4
4.5
0.0
0
2
4 6 Cap_Z [nF]
8
10
Fig. 6. Shutdown Time vs. Ctimer Characteristics
Fig. 7. Power on Reset Time vs. Cap_Z Characteristics (Rseries = 10k)
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CXB1549Q
VCC = 0V VEE = -3.3V RL = 25 Ta = 27C IQ = 30mA Single input Pattern = PRBS223-1 Data Rate 1.25Gbps
Ch.1 :150mV/div, Offset: -300mV Bandwidth: 20.0GHz Time Base : 200ps/div
Fig.8. Electrical output waveform
2
1
VCC = 0V VEE = -3.3V FP-LD ( = 1330nm) Ta = 27C Single Input Pattern = PRBS223-1 Data Rate 1.06Gbps Filter (Cut Off 700Mbps) Mask: FC1063
3 Ch.2 :5.0mV/div, Offset: 12.8mV Bandwidth: 12.4GHz Time Base:200ps/div
Fig.9. Optical output waveform
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CXB1549Q
CXB1549Q PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME VCC4 VEE4 BiasAdj SBias Bias VEE5 Q QBX VEE1 VEE1 VCC1 VEE1 DrvMon DrvAdj CompA CompB Timer NC TM ADCDis PIN# 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN NAME VEE2 DB D VCC2 VBB Indicate Tset RSB RS LDAlmB LDAlm SDN SDNB VREF TEST_PIN VCC3 CapZ VEE3 APCOut RsetPD
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CXB1549Q
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
9.0 0.4 + 0.4 7.0 - 0.1 30 21
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1
31
20
A
40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1
11
10 0.24 M
0 to 10
0.5 0.2
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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